vishay siliconix spice device model SUM90P10-19L p-channel 100-v (d-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 10-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www. vi s h a y .com document number: 74169 s-61262 ? rev . a, 24-jul-06
v ishay siliconix spice device model SUM90P10-19L specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n simulated data measu red data unit static gate threshold voltage v gs(t h ) v ds = v gs , i d = ? 250 a 1 . 9 v on-state drain current a i d ( on) v ds = ? 5 v, v gs = ? 10 v 3 1 3 a v gs = ? 10 v, i d = ? 20 a 0 . 0 1 5 7 0 . 0 1 5 6 drain-source on-state resistance a r d s (on) v gs = ? 4.5 v, i d = ? 15 a 0 . 0 1 7 3 ? forw ard voltage a v sd v ds = ? 15 v, i f = ? 20 a 0.88 0.80 v dy namic b input capacitance c iss 1 0 7 1 0 1 1 1 0 0 output capacitance c oss 5 5 6 7 0 0 rev e rse transfe r capacitance c rs s v ds = ? .50 v, v gs = 0 v, f = 1 m h z 1 2 1 4 1 6 9 0 pf v ds = ? 50 v, v gs = ? 10 v, i d = ? 90 a 2 1 7 t o tal gate c harge c q g 1 1 7 9 7 gate-source charge c q gs 4 2 4 2 gate-drain charge c q gd v ds = ? 50 v, v gs = ? 4.5 v, i d = ? 90 a 5 1 5 1 nc not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. c. independent of operat ing temperature. 2 www. vi s h a y .com document number: 74169 s-61262 ? rev . a , 24-jul-06
vishay siliconix spice device model SUM90P10-19L comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) 3 www. vi s h a y .com document number: 74169 s-61262 ? rev . a , 24-jul-06
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